Field of the Invention
Embodiments of the present invention generally relate to non-volatile memory devices, and more particularly to a charge trap flash memory device that yields minimum endurance degradation and a maximum program/erase window.
Description of the Related Art
Non-volatile memory (NVM) devices are electronic memory devices that retain their content when external power is removed. These devices are used in a wide variety of commercial and military electronic devices and equipment, such as hand-held telephones, radios and digital cameras. An NVM device comprises an insulating barrier, which can include multiple dielectric layers, located between a charge supply region and a charge storage region. The charge storage region can take the form of a floating gate structure or a charge trapping layer. Programming such NVM devices is accomplished by tunneling charge carriers of a first type such as electrons from the charge supply region, through the insulating barrier, toward the charge storage region.
One type of NVM device is flash memory. Flash memory devices can be further divided into floating gate flash memory and charge trap flash (CTF) memory. In floating gate memory devices, a floating gate of a metal layer or a metal-like layer is used as the charge storage layer. In CTF memory devices, such as in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory devices, a charge trapping dielectric layer is used.
Essentially, a SONOS memory cell is a conventional n-channel metal-oxide-semiconductor transistor (NMOS) with a gate dielectric of a thermal oxide layer of about 2-7 nm thickness, a silicon nitride layer of about 3-12 nm thickness and a second oxide layer with a thickness of between 5 nm and 20 nm. The thin oxide layer is an exemplary tunneling layer and the nitride layer is an exemplary charge trapping layer. At a positive gate bias, electrons can tunnel from the substrate through the ultra thin oxide layer to the nitride layer, where they are subsequently trapped. Silicon nitride, for example, has an intrinsic property of trapping charge (electrons or holes).
In SONOS memory devices, the trapped charges create a threshold voltage shift of the transistor. The threshold voltage Vth varies depending on whether the NVM device is in the program state, wherein charges (electrons) are injected into the charge trapping layer, or in the erase state, wherein electrons leave (or holes enter) the charge trapping layer. This state in turn varies the gate voltage level needed to allow a certain current level to conduct through the channel. Hence, operation of charge trapping NVM semiconductor devices is based on the threshold voltage Vth being varied by charges trapped or stored in a charge trapping layer.
NVM devices that use charge trapping as a charge storage mechanism instead of a floating gate are becoming more and more prevalent. Such devices store charge in a charge trapping layer, such as a silicon nitride layer sandwiched between two oxide layers or, as an alternative, in nanocrystals. Charge trapping NVM devices are becoming more prevalent partially because they are believed to have considerable potential for use in future complementary metal-oxide-semiconductor generations, particularly for technologies with dimensions of 90 nm and smaller. One difference between charge trapping devices and floating gate devices is that with charge trapping devices electrons are trapped in energy minima caused by imperfections in the charge trapping layer or, in the case of nanocrystal memories, on nanocrystals embedded in a gate oxide. These energy minima act as localized charge storage sites that are isolated from each other in which charge is trapped and stored. In the case of electrons, for example, the free electron energy levels associated with such imperfections and/or nanocrystals are below the free electron energy levels of the surrounding material, thereby creating energy wells and trapping free electrons therein at the locations of the imperfections and/or nanocrystals.
As mentioned, one reason for the growing interest in charge trapping devices is that such devices are relatively easy to scale with associated reductions in physical geometries for future semiconductor processing technology generations. For instance, the use of charge trapping devices eliminates floating gate patterning issues, such as those related to lithography, overlay and topography. Moreover, charge trapping devices may be programmed and erased using lower voltages than floating gate devices implemented in the same semiconductor process. The ability to use lower voltages is important, especially in embedded memories, since the market continues to demand devices that use lower operating voltages and have reduced power consumption. Another requirement is endurance which needs to meet different specifications for different application. A stringent endurance requirement is needed for solid state drives which is a growth sector for NAND Flash, (see JEDEC specifications for NAND performance).
However, prior art charge trapping NVM devices have certain disadvantages. One such drawback relates to the relatively poor erasing efficiency characteristic of these memory devices that prevents them from meeting backwards compatibility requirements of a ˜10−4 second erasing time at a negative (around −3 V) threshold voltage Vth. The known charge trap flash memory devices have this problem because of electron back tunneling through the blocking layer. Such back tunneling causes the erase threshold voltage Vth to not drop off sufficiently or sufficiently quickly in known SONOS devices. For example, the erase threshold voltage Vth in known devices should typically drop from about 1 V to about −3 V during the desired erase time of about 10−3 seconds. The erase threshold voltage Vth may then continue to decrease or may increase, especially when the gate bias is about −17 V to −15 V.
Another disadvantage is the limited data retention capability of known charge trapping devices. Data retention is the ability of an NVM device to retain data programmed into individual memory cells. This limited data retention capability is due, in part, to the use of thin dielectrics between the substrate (e.g., the charge supply region) and the charge trapping layer. While the use of a thicker conventional tunnel dielectric such as SiO2 would improve this data retention capability, this improvement would come at the expense of worsened erase saturation for the devices and, consequently, the duration of a program/erase window (increased duration) for current charge trapping NVM devices. Erase saturation is the inability to completely remove or compensate for the charge stored in the charge storage region of a charge trapping NVM device after programming the device. Therefore, alternative approaches for implementing charge trapping NVM devices are desirable.
Retention and memory window (before and after cycling or endurance) are two challenges associated with CTF performance. Silicon nitride trap layer engineering by changing the composition (for example Si:N ratio) provides an important trade-off. As the atomic percent N in SiNx:H (hydrogen is frequently incorporated from precursors in the range of about 0 to about 15 atomic percent) is increased two trends are observed, the memory window decreases and the retention is strongly enhanced. In addition it has been observed that the memory window degradation after endurance increases (worsens) with the increase in the nitrogen content.
The profitability of CTF technology is driven by multi-level cell (MLC) operation which requires a large memory window. On the other hand, retention is a core specification. Due to conflicting trends, a trade-off is present. Nitrogen-rich nitride can produce satisfactory retention but enhanced endurance memory window degradation. An ideal solution would provide satisfactory retention and improve endurance degradation for maximum memory window for reliable MLC operation.
Thus, there is a need for an optimal NVM semiconductor device that simultaneously provides minimum endurance degradation and a maximum program/erase window, and a corresponding manufacturing method.